Analog-to-digital converters (ADCs) are used in electronic devices to convert an analog signal to a digital signal. ADCs can be designed in a number of different architectures. One conventional ADC architecture is the pipeline ADC. A pipeline ADC, as illustrated in FIG. 1A, operates on discrete time signals, and therefore mathematical operations, sample-and-hold, DAC, and gain can all be performed in a single switched-capacitor circuit such as an MDAC. An MDAC is a high-gain and high-bandwidth amplifier with capacitive feedback.
In analog design, it is ideal to minimize power consumed and maximize speed. However, in modern high speed switched-capacitor CMOS pipeline ADCs, the MDAC is a major contributor in power consumption and limitation of clock rate. Current architectures of MDAC amplifiers, whether single- or multi-stage, have inherently limited efficiency because loop-gain is attenuated by significant loss in the feedback, in part due to significant parasitic capacitors on the summation node (such as node N3 of FIG. 1C). If the loop-gain can be increased with a topology change or reduction of the parasitic capacitance, then a more efficient amplifier can be built where settling time is reduced (increased bandwidth) and power can be minimized.
Conventional techniques have limitations in the settling response due to non-dominate poles. In addition, these non-dominate poles are typically inside a global feedback loop with a sampling capacitor and a feedback capacitor, which greatly increases the sensitivity of the system and the difficulty of controlling the system. Thus, there also exists a need to reduce the sensitivity of the system and improve the stability of the system, for example by removing the poles from inside the feedback loop.